A critical requirement in many electronic system designs is an ability to retrieve data that has been saved in electronic memory configuration when a power failure or other power reduction event occurs. Such a power reduction event may occur, for example, as a result of a total system power failure or merely a temporary drop in a specified system power level. In any event, such a power reduction event typically causes data that has been stored in an electronic memory configuration to be lost, unless the electronic memory configuration is a non-volatile electronic memory configuration. However, non-volatile electronic memory configurations are typically very expensive and/or too slow to accommodate data storage requirements. Regarding the latter, flash memory devices, for example, are non-volatile in nature, but the speed at which they store data is too slow to be used as a primary memory in most high-speed electronic systems. Regarding the former, non-volatile electronic memory configurations typically require multiple components, some of which are typically very costly price-wise, while the combination of which are typically very costly in terms of physical circuit board space.
For example, referring to FIG. 1, there is shown a conventional non-volatile electronic memory configuration 100 comprising a high speed, low power, static random access memory device (SRAM) 102, a signal switch 104, a power switch 106, a voltage detector 108, and an auxiliary power source 110. The configuration 100 operates by allowing data to be stored in the SRAM 102 using a data bus (D), an address bus (A), a read/write control signal (R/W), and a chip select control signal (CS) in a conventional manner when a power supply (Vdd) is within a typical operating voltage range (e.g., 4.9-5.1 volts). In such a case, the voltage detector 108 detects that the power supply (Vdd) is within the typical operating voltage range (e.g., 4.9-5.1 volts) and controls the power switch 106 such that it is configured to connect the power supply (Vdd) to the SRAM 102. In this case, the voltage detector 108 also controls the signal switch 104 such that it is configured to connect the chip select control signal (CS) to the SRAM 102.
However, when the voltage detector 108 detects that the power supply (Vdd) is outside of the typical operating voltage range (e.g., 4.9-5.1 volts), it controls the power switch 106 such that it is configured to connect the auxiliary power source 110 to the SRAM 102, thereby allowing previously stored data to be retained in the SRAM 102. In this case, the voltage detector 108 also controls the signal switch 104 such that it is configured to disconnect the chip select control signal (CS) from the SRAM 102, thereby preventing corrupt data from being written to the SRAM 102.
The configuration 100 obviously requires multiple components, of which most are typically very expensive. For example, the SRAM 102 is much more expensive than a dynamic random access memory device (DRAM) of comparable storage size. Also, the auxiliary power source 110 typically comprises an expensive battery or very large capacitor, or both, for providing auxiliary power. Further, batteries have only a limited life, and capacitors typically degrade over time. Additionally, the combination of all of these components typically consume considerable physical circuit board space.
In view of the foregoing, it would be desirable to provide a high speed non-volatile electronic memory configuration which overcomes the above-described inadequacies and shortcomings in an efficient and cost effective manner.